To properly display video on a television screen or computer screen, synchronization must be made with horizontal and vertical synchronization signal data within a video signal. This facilitates horizontal and the vertical positioning for display monitors and television screens so that the system can identify which data needs to be put into a frame buffer for a particular line and at what particular time. With composite video input, the horizontal synchronization data, vertical synchronization data, blanking data and video data is typically included in one analog signal and there is a need to separate out this information. Where the analog video signal is noisy, horizontal synchronization data may include noise causing visual jitters to appear on a display screen if not properly filtered out.
One method for filtering out the noise in analog horizontal synchronization information includes detecting a rising edge and falling edge of a horizontal synchronization pulse. However, such systems typically still allow jitter to occur since filtering may be inadequate so that multiple detections can occur where the analog video signal is very noisy. With such systems, it can be difficult to determine exactly when a horizontal synchronization pulse begins.
Other systems, such as analog television decoders typically measure the width of a horizontal synchronization pulse and attempt to determine a center of the pulse to obtain an accurate start and end of the synchronization pulse using a voltage controlled oscillator as known in the art. However, such analog systems may be unnecessarily costly for digital applications. Digital video chips are typically designed to be small and inexpensive and also operate at high speeds to provide high quality synchronization to facilitate enhanced graphic capability. For example, where analog video from a VCR or camera is input to a computer, a video decoder may convert the analog video to a Y, U, V chroma and luminance data stream for display on the computer monitor, while also encoding the Y, U, V information for output to a television screen. Such chips typically must be accurate and cost competitive.
Another method for detecting horizontal synchronization information includes determining only one fractional component of a detected horizontal synchronization edge in the instances where the actual edge occurs between clock cycles. However, with such single edge fractional compensation, a horizontal synchronization signal phase lock loop may lock on a wrong edge which can cause a visually detectable image shift. Hence single edge fractional compensation may not provide adequate synchronization for high quality display applications.
Also, where the analog video signal is weak, horizontal synchronization detection circuits may not detect small levels of video input even after amplification from automatic gain control circuitry since slice threshold levels are typically static. Failure to detect the horizontal synchronization signal can result in loss of video display data.
Consequently, there exists a need for a digital horizontal synchronization pulse phase detection circuit and method that provides suitable horizontal phase detection for a horizontal synchronization phase lock loop to enhance display quality of video information.